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* ADDITIONAL NOTES: 
* //The Processor starts with the Internal oscillator without PLL enabled and then the Clock is switched to PLL Mode.
*
**********************************************************************/

#if defined(__dsPIC33F__)
#include "p33Fxxxx.h"
#elif defined(__PIC24H__)
#include "p24Hxxxx.h"
#endif


#define FCY				36500000
#define BAUDRATE        9600                   
#define BRGVAL          ((FCY/BAUDRATE)/16)-1


_FOSCSEL(FNOSC_FRC );		// FRC Oscillator 
_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF  & POSCMD_NONE); 
								// Clock Switching is enabled and Fail Safe Clock Monitor is disabled
								// OSC2 Pin Function: OSC2 is Clock Output
								// Primary Oscillator Mode: Disabled


_FWDT(FWDTEN_OFF);              // Watchdog Timer Enabled/disabled by user software
								// (LPRC can be disabled by clearing SWDTEN bit in RCON register

//long tonegen(int samp, int tone, int phase,long *tfBuff);


//-------------Funcion Ppal-------------

int main (void)
{

// Configure Oscillator to operate the device at 40Mhz
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 7.37M*40/(2*2)=80Mhz for 7.37M input clock
	PLLFBD=38;					// M=40
	CLKDIVbits.PLLPOST=0;		// N1=2
	CLKDIVbits.PLLPRE=0;		// N2=2
	OSCTUN=0;					// Tune FRC oscillator, if FRC is used

// Clock switch to incorporate PLL
	__builtin_write_OSCCONH(0x01);		// Initiate Clock Switch to
													// FRC with PLL (NOSC=0b001)
	__builtin_write_OSCCONL(0x01);		// Start clock switching
	while (OSCCONbits.COSC != 0b001);	// Wait for Clock switch to occur	

// Wait for PLL to lock
	while(OSCCONbits.LOCK!=1) {};
  
    // Configure the Analog functional pins as digital 
	AD1PCFGL=0xFFFF;
	AD1PCFGH=0xFFFF;

	 dciInit();
	 si3000Init();

	while(1);
	
 }  // End of main


